In accordance with development for an increased degree of integration of a semiconductor integrated circuit, capacitance between interconnects corresponding to parasitic capacitance between metal interconnects is increasing. The increase of the capacitance between interconnects increases interconnect delay time, and as a result, it prevents performance improvement of the semiconductor integrated circuit. It is noted that the interconnect delay time is so-called RC delay that is in proportion to a product of the resistance of a metal interconnect and the capacitance between interconnects.
Accordingly, in order to reduce the interconnect delay time, it is necessary to lower the resistance of a metal interconnect or to reduce the capacitance between interconnects.
Therefore, IBM and Motorola have reported semiconductor integrated circuit devices in which a copper material is used as the material for interconnects instead of an aluminum-based alloy material in order to lower the resistance of the metal interconnects. The specific resistance of the copper material is approximately ⅔ of that of the aluminum-based alloy material. Therefore, when the copper material is used as the material for the interconnects, the interconnect delay time is reduced to approximately ⅔ in simple calculation as compared with the case where the aluminum-based alloy material is used as the material for the interconnects. Accordingly, the transfer time on an interconnect can be increased by 1.5 times.
However, when the degree of integration of semiconductor integrated circuit devices is further increased, the interconnect delay time is increased, and therefore, it is apprehended that the increase of the transfer time of an interconnect will be limited even when the metal is used as the material for the interconnect. Furthermore, copper used as the interconnect material has the lowest specific resistance next to silver, and hence, even if a metal interconnect made of a silver material instead of a copper material is used, the resistance of the metal interconnect can be merely slightly lowered.
Therefore, in order to cope with further increase of the degree of integration of semiconductor integrated circuit devices, it is significant not only to lower the interconnect resistance but also to reduce the capacitance between interconnects, and for reducing the capacitance between interconnects, it is necessary to reduce the dielectric constant of an interlayer insulating film.
A silicon oxide film is conventionally used as an interlayer insulating film, and since the dielectric constant of a silicon oxide film is approximately 4 through 4.5, it is difficult to use such a silicon oxide film as an interlayer insulating film of a more highly integrated semiconductor integrated circuit device. Therefore, as an interlayer insulating film with a lower dielectric constant than a silicon oxide film, a silicon oxide film including fluorine, a carbon-containing silicon oxide film, a low dielectric constant SOG (spin on glass) film and an organic polymer film have been proposed.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-349084